The performance of a Dynamic Random Access Memory (DRAM) memory system is dependent on the accesses that are presented to it. A system with a high page-hit rate generally performs better than one with a lower page-hit rate. In order to improve the page hit rate, a concept of address tiling is introduced. Essentially, address tiling is the transformation on the system address bits to generate a memory address such that the page hit rate in the DRAM is improved. The memory scheduler attempts to improve DRAM utilization by preferring requests that hit the page over those that cause a page miss.
Channel interleaving may also improve DRAM performance. Chopping of burst requests by hardware in an integrated circuit can relieve the initiator from knowing the exact details of how the DRAM is organized.